The Simple Differential OTA

Analysis

Christian Enz

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

# Initialization¶

# Introduction¶

Schematic of the simple differential OTA.

This notebook presents the analysis of the simple differential OTA shown in the above figure. We can distinguish the case where M1a-M1b are in the common substrate (left schematic) and the case where M1a-M1b are in a separate well (right schematic). We will see below that in differential mode and assuming a perfect matching (i.e. M1a identical to M1b and M2a identical to M2b), the effects of the source transconductances on the common substrate schematic are actually canceled.

We will start with some considerations on the large-signal operation, followed by the small-signal analysis, and finally by the noise analysis.

# Large-signal Analysis¶

## Voltage Transfer Characteristic¶

Since there are two input terminals, several large-signal voltage transfer characteristics can be derived. In many situations, one of the two input terminals will be maintained at a constant common mode voltage (typically $V_{DD}/2$) while the other is connected to some feedback network. If for example the negative input is set constant, at for example the middle of the supply voltage $V_{DD}/2$, the positive input can be swept from ground to $V_{DD}$. The output voltage will change from ground to $V_{DD}$ as well. The amplifier will provide some gain for $V_{in+}$ ranging close to $V_{in-}$. Outside this high gain region, the output voltage will saturate either to $V_{DD}$ for $V_{in+}$ larger than $V_{in-}$, or to 0 for $V_{in+}$ smaller than $V_{in-}$. Under the above conditions, the maximum output voltage $V_{out,max}$ in the linear range is limited by M2b going out of saturation

\begin{equation*} V_{out,max} = V_{DD} - V_{DSsat2b}. \end{equation*}

On the other hand, the minimum output voltage $V_{out,min}$ of the linear range is limited by M1b going out of saturation and depends linearly on the common-mode voltage set on $V_{in-}$ according to

\begin{equation*} V_{out,min} = V_{DSsat3} - V_{GS1b} + V_{in-}. \end{equation*}

If M1b is biased in weak inversion then $V_{DSsat1b} \cong 4 U_T \cong 100 mV$. The value of $V_{GS1b}$ depends wether M1a-M1b are in a separate well or are in the common substrate.

### M1a-M1b in a separate well¶

In the case M1a-M1b are in a separate well, then $V_{S1} = 0$ and hence $V_{GS1b} \cong V_{T0n}$. The minimum output voltage in the linear range is then given by

\begin{equation*} V_{out,min} = 4 U_T - V_{T0n} + V_{in-}. \end{equation*}

As long as M2b remains in saturation (i.e. for $V_{out} < V_{out,max}$), the currents flowing in M1a and M1b are imposed equal by the current mirror. When decreasing $V_{in+}$ and for $V_{out}$ below $V_{out,min}$, the current in M1b is equal to $I_b/2$ as long as M3b remains in saturation. The gate voltage of M1b is equal to $V_{in-}$ and the source voltage of M1a and M1b follows $V_{in+}$ with a shift of $V_{GS1a} \cong V_{T0n}$. Since the current is imposed equal to $I_b/2$ by the current mirror, the increase in $V_{G1b}$ has to be compensated by a decrease of the drain voltage, which is the only remaining degree of freedom in M1b. This decrease of the drain voltage of M1b brings it in the linear region with a drain-to-source voltage close to zero. In such condition, the output voltage is about equal to the source voltage which decreases linearly with the positive input voltage

\begin{equation*} V_{out} \cong V_1 = V_{in+} - V_{GS1a} \cong V_{in+} - V_{T0n}. \end{equation*}

These considerations lead to the large-signal characteristic shown below which is obtained from simulation in the case of a $0.18\,\mu m$ process with $V_{DD}=1.8\,V$.

Large-signal output voltage versus positive input voltage transfer characteristic for various values of the negative input voltage (M1a-M1b in separate well).

### M1a-M1b in the common substrate¶

In the case M1a-M1b are in the common substrate, the gate-to-source voltage of M1b will depend on the source voltage $V_S$ of M1a and M1b according to \begin{equation*} V_{GS1b} = V_{G1b}-V_S = n_{1b} V_{P1b} + V_{T0n} - V_S = n_{1b} (V_{P1b}-V_S) + V_{T0n} + (n_{1b}-1) V_S, \end{equation*} where the approximation $V_{P1b} \cong (V_{G1b}-V_{T0n})/n_{1b}$ has been used. In the case M1a-M1b are biased in weak inversion, $V_{P1b}-V_S \cong 0$ and therefore \begin{equation*} V_{GS1b} \cong V_{T0n} + (n_{1b}-1) V_S. \end{equation*} The source voltage is also given by \begin{equation*} V_S = -V_{GS1b} + V_{in-} \cong - V_{T0n} - (n_{1b}-1) V_S + V_{in-} \end{equation*} from which we can deduce $V_S$ as \begin{equation*} V_S \cong \frac{V_{in-}-V_{T0n}}{n_{1b}}. \end{equation*} The gate-to-source voltage of M1b then writes \begin{equation*} V_{GS1b} \cong V_{in-} - \frac{V_{in-}-V_{T0n}}{n_{1b}} \end{equation*} Finally, the minimum output voltage is given by \begin{equation*} V_{out,min} \cong V_{in-} + 4 U_T - V_{GS1b} = \frac{V_{in-}-V_{T0n}}{n_{1b}} + 4 U_T. \end{equation*} Below $V_{out,min}$, the output voltage will decrease linearly with $V_{in+}$ with a slope $1/n_{1a}$ \begin{equation*} V_{out} \cong \frac{V_{in+}-V_{T0n}}{n_{1a}}. \end{equation*}

This is confirmed by the simulations results shown below.

Large-signal output voltage versus positive input voltage transfer characteristic for various values of the negative input voltage (M1a-M1b in common substrate).

## Input Common Mode Voltage Range¶

The minimum input common-mode voltage $V_{ic,min}$ corresponds to the situation where M3b is getting out of saturation, which occurs when $V_S=V_{DSsat3b}$ \begin{equation*} V_{ic,min} = V_{GS1} + V_{DSsat3b}. \end{equation*}

The maximum input common-mode voltage $V_{ic,max}$ corresponds to the situation where M1a gets out of saturation. Assuming that the differential pair is biased in weak inversion, the saturation voltage of M1a-M1b is about $4\,U_T$. We then have \begin{equation*} V_{ic,max} = V_{GS1a} - V_{DSsat1a} - V_{SG2a} + V_{DD} \cong V_{GS1a}- 4 U_T - V_{SG2a} + V_{DD}. \end{equation*} The gate-to-source voltage of M1a $V_{GS1a}$ depends whether M1a and M1b are in a separate well or in the common substrate.

### M1a-M1b in a separate well¶

In the case M1a-M1b are in a separate well, $V_{GS1a} \cong V_{T0n}$, and the common mode input voltage limits are given by \begin{align} V_{ic,min} &\cong V_{T0n} + V_{DSsat3b}\\ V_{ic,max} &\cong V_{T0n} - 4 U_T - V_{SG2a} + V_{DD}. \end{align} The common mode input voltage range $\Delta V_{ic}$ is then given by \begin{equation*} \Delta V_{ic} \triangleq V_{ic,max} - V_{ic,min} \cong V_{DD} - V_{SG2} - 4 U_T - V_{DSsat3b}. \end{equation*} The above equation shows that although it is appropriate to bias M2a-M2b and M3a-M3b in strong inversion, choosing a too large saturation voltage will reduce the available common mode input range.

### M1a-M1b in a common substrate¶

In the case M1a-M1b are in a common substrate, the gate-to-source voltage of M1a is given by \begin{equation*} V_{GS1a} \cong V_{T0n} + (n_{1a}-1) \cdot V_S \end{equation*} The minimum input common-mode voltage $V_{ic,min}$ corresponds to M3b getting out of saturation, which occurs when $V_S=V_{DSsat3b}$. We then have \begin{equation*} V_{ic,min} = V_{GS1a} + V_{DSsat3b} = V_{T0n} + (n_{1a}-1) V_{DSsat3b} + V_{DSsat3b} = V_{T0n} + n_{1a} \cdot V_{DSsat3b}. \end{equation*} The gate-to-source voltage of M1a is given by \begin{equation*} V_{GS1a} \cong V_{ic}-V_S \end{equation*} from which we get the source voltage when M1a is at the saturation limit \begin{equation*} V_S \cong V_{ic,max} - V_{GS1a} = V_{ic,max} - V_{T0n} - (n_{1a}-1) V_S \end{equation*} and hence \begin{equation*} V_S \cong \frac{V_{ic,max} - V_{T0n}}{n_{1a}}. \end{equation*} Replacing in the above equation results in \begin{equation*} V_{GS1a} \cong V_{ic,max} - \frac{V_{ic,max} - V_{T0n}}{n_{1a}} \end{equation*} and finally \begin{equation*} V_{ic,max} \cong n_{1a} \cdot (V_{DD} - V_{SG2a} - 4 U_T) + V_{T0n}. \end{equation*}

Finally, the common mode input voltage range $\Delta V_{ic}$ is given by \begin{equation*} \Delta V_{ic} \cong n_{1a} \cdot (V_{DD} - V_{SG2a} - 4 U_T - V_{DSsat3b}). \end{equation*}

From the above equations, we see that having M1a-M1b in the common substrate gives a common mode input voltage range $n_{1a}$ larger than having them in a separate well. Since the upper limit is identical, it comes from the fact that the slope of the output voltage versus $V_{in+}$ is $1/n_{1a}$ which is slightly smaller than $1$.

## Slew-Rate¶

Assuming that the differential pair is biased in weak inversion, when the magnitude of the differential voltage becomes larger than about $4 U_T$, the magnitude of the output current saturates to $2 I_b$. The OTA then behaves like a current source of value $2 I_b$ loaded by the load capacitance $C_L$. The rate of voltage change across the load capacitance is therefore limited to a maximum given by \begin{equation*} SR \triangleq \left|\frac{d V_{out}}{dt}\right|_{max} = \left|\frac{I_{out}}{C_L}\right|_{max} = \frac{2 I_b}{C_L}. \end{equation*} For a given load capacitance and a given available transient time, the slew-rate $SR$ often determines the minimum required bias current.

# Small-signal analysis¶

Small-signal schematic of the simple OTA.

The corresponding small-signal schematics are shown in the above figure. We see the source transconductances in the left schematic, which are controlled by the common voltage at the source $\Delta V_1$. We now first look at the differential mode of operation.

## Differential mode¶

Simplified small-signal schematic of the simple OTA neglecting all output conductances.

In order to derive the differential transadmittance, we first will simplify the small-signal schematic by considering that the output conductances are much smaller than the transconductances $G_{ds} \ll G_m < G_{ms}$ for all transistors. This leads to the simplified small-signal schematics shown in the above figure.

The differential transadmittance is defined as \begin{equation*} Y_{md} \triangleq \frac{I_{out}}{V_{id}}, \end{equation*} where $V_{id} \triangleq V_{in+}-V_{in-}$ is the differential input voltage and $I_{out}$ the output current. Note that in the small-signal schematic, the output node has been connected to the ac ground. The output conductance of transistor M2b $G_{ds2b}$ is then grounded and can therefore be neglected. Also, the output conductance of transistor M2a $G_{ds2a}$ is in parallel with its transconductance $G_{m2a}$ and since usually $G_{ds2a} \ll G_{m2a}$, it can also be neglected. Assuming a perfect matching, i.e. $G_{m1a}=G_{m1b}=G_{m1}, G_{ms1a}=G_{ms1b}=G_{ms1}, G_{m2a}=G_{m2b}=G_{ms2}$, the differential transadmittance is then given by \begin{equation*} Y_{md} = G_{m1} \frac{1+s \tau_2/2}{1+s \tau_2} = G_{m1} \cdot \frac{1+s/(2\omega_2)}{1+s/\omega_2} \end{equation*} where $\tau_2 = 1/\omega_2 \triangleq C_2/G_{m2}$ is the time constant introduced by the current mirror M2a-M2b due to the parasitic capacitance $C_2$ at node 2. Note that the above equation for $Y_{md}$ is valid for both M1a-M1b in a separate well and in a common substrate. This is due to the fact that in differential mode and assuming a perfect matching, the common source node 1 does not change and can be considered as an ac ground. This means that $\Delta V_1=0$ and hence the two small-signal circuits of the left and right schematic become identical.

A transfer function where the zero is at double the frequency of the pole like for $Y_{md}$, is called a doublet. The left hand side (LHS) zero cancels the effect of the pole.

The magnitude of $Y_{md}$ normalized to the low-frequency value $G_{m1}$ versus the frequency is shown below.

Magnitude of the transadmittance Ymd normalized to the transconductance Gm1 versus the frequency.

For $\omega < \omega_2$, both current branches of the differential pair are active. On the other hand, for $\omega > \omega_2$, the voltage at node 2 is low-pass filtered and ac grounded and therefore the small-signal current coming from transistor M1a is not copied to the output. The output current is hence only coming from transistor M1b, resulting in half the low-frequency transconductance corresponding to the -6 dB shown in the above plot.

The differential mode voltage transfer function $A_{vd}$ is simply given by \begin{equation*} A_{vd} \triangleq \frac{V_{out}}{V_{id}} = Y_{md} \cdot Z_L \end{equation*} where $Z_L$ is the output load impedance. In the case the output load is only capacitive \begin{equation*} Y_L \triangleq \frac{1}{Z_L} = G_o + s\,C_L \end{equation*} where $G_o$ is the total conductance at the output node $G_o = G_{ds1b} + G_{ds2b}$. This results in \begin{equation*} A_{vd} = \frac{G_{m1}}{G_o + s C_L} \cdot \frac{1+s/(2\omega_2)}{1+s/\omega_2} = A_{dc} \cdot \frac{1+s/(2\omega_2)}{(1+s/\omega_0) (1+s/\omega_2)} \end{equation*} where $A_{dc} \triangleq G_{m1}/G_o$ is the DC gain, $\omega_o \triangleq G_o/C_L$ the dominant pole and $\omega_2 \triangleq G_{m2}/C_2$ the non-dominant pole. The Bode plot of the differential voltage transfer function is plotted below.

Magnitude and phase of the open-loop differential voltage gain versus frequency.

Assuming that the non-dominant pole $\omega_2$ is much higher than the unity gain frequency $\omega_u$ (or gain-bandwidth product $GBW$), the latter is then given by \begin{equation*} \omega_u = GBW = A_{dc} \cdot \omega_0 = \frac{G_{m1}}{G_o} \cdot \frac{G_o}{C_L} = \frac{G_{m1}}{C_L}. \end{equation*} Note that the phase reaches a minimum for $\omega= \sqrt{2} \omega_2$ \begin{equation*} \Phi_{min} = -\frac{\pi}{2} + arctg(\sqrt{2}/2) - arctg(\sqrt{2}) \cong -109.5^\circ. \end{equation*}

## Common mode¶

In common mode, the differential voltage is zero $V_{id}=0$ and both inputs are controlled by the common mode voltage $V_{ic}$. The common mode transadmittance $Y_{mc}$ is defined as \begin{equation*} Y_{mc} \triangleq \frac{I_{out}}{V_{ic}} = -G_{m1} \cdot \frac{s^2 \tau_1 \tau_2}{(1+s\tau_1)(1+s\tau_2)} = -G_{m1} \cdot \frac{s^2/(\omega_1 \omega_2)}{(1+s/\omega_1)(1+s/\omega_2)} \end{equation*} where $\tau_1$ corresponds to the time constant of the common source node 1 of the differential pair given by \begin{equation*} \tau_1 = \frac{1}{\omega_1} = \frac{C_1}{2 G_{m1}} \end{equation*} for M1a-M1b in a separate well and \begin{equation*} \tau_1 = \frac{1}{\omega_1} = \frac{C_1}{2 G_{ms1}} = \frac{C_1}{2 n_1 G_{m1}} \end{equation*} for M1a-M1b in a common substrate. $\tau_2$ corresponds to the time constant of the current mirror node 2 and is given by \begin{equation*} \tau_2 = \frac{1}{\omega_2} \triangleq \frac{C_2}{G_{m2}}. \end{equation*}

From the above expression, we see that $Y_{mc}$ has a high-pass charactersitic and is therefore equal to zero at DC. Note that it is actually limited by the conductance at node 1 $G_1$ and the mismatch in the differential pair and the current mirror.

At high frequency (i.e. $\omega \gg \omega_1$ and $\omega \gg \omega_2$), nodes 1 and 2 are ac grounded and the output current is directly provided by M1b, so that $Y_{mc}$ becomes equal to $-G_{m1b}$.

The common-mode rejection ratio (CMMR) is then given by \begin{equation*} CMRR \triangleq \frac{Y_{md}}{Y_{mc}} = -\frac{(1+s\tau_1)(1+s\tau_2/2)}{s^2\tau_1\tau_2} = -\frac{(1+s/\omega_1)(1+s/(2\omega_2)}{s^2/(\omega_1\omega_2)}, \end{equation*} which, assuming a perfect matching, is ideally infinite at low frequency and degrades for increasing frequency to reach -6dB at high frequency.

# Noise Analysis¶

In order to calculate the output noise current $I_{nout}$, the input terminals are AC grounded. The small-signal equivalent circuit including the noise sources of all the transistors are shown below.

Simplified small-signal noise schematic. a) M1a-M1b in common substrate. b) M1a-M1b in separate well.

The left schematic corresponds to all N-channel transistors in the same substrate whereas the right schematic corresponds to M1a-M1b in a separate well . Note that all the output conductances have been neglected. Since we want to calculate the noise at low-frequency (meaning for $\omega < \omega_2$), we can also neglect the parasitic capacitances $C_1$ and $C_2$. If the differential pair is assumed to be perfectly matched, then the two currents generated by transconductances $G_{m1a}$ and $G_{m1b}$, or $G_{ms1a}$ and $G_{ms1b}$ in the above schematics are equal. If the current mirror is also assumed to be perfectly matched (i.e. $G_{m2a}=G_{m2b}=G_{m2}$), then the current coming from M1a is mirrored at the output and compensated by the current coming directly from M1b. Therefore, the transconductances $G_{m1a}$ and $G_{m1b}$ (respectively $G_{ms1a}$ and $G_{ms1b}$) have no effect on the output current. They can therefore be neglected. Assuming again perfect matching, the noise currents $I_{n3a}$ and $I_{n3b}$ coming from transistors M3a and M3b split equally between the two branches and produce no net current at the output neither. They can therefore also be neglected. Finally, the output noise current is simply given by \begin{equation*} I_{nout} = I_{n1a} - I_{n1b} - I_{n2a} + I_{n2b}. \end{equation*} This means that the transfer functions at low-frequency from each of the noise sources to the output current is simply equal to $\pm 1$. Note that the sign is of no importance since for noise we are only interested by the square magnitude of the transfer functions.

The power spectral density (PSD) of the output noise current is then given by \begin{equation*} S_{nout}(f) = 4kT \cdot G_{nout}(f), \end{equation*} with \begin{equation*} G_{nout}(f) = G_{n1a}(f) + G_{n1b}(f) + G_{n2a}(f) + G_{n2b}(f) = 2(G_{n1}(f) + G_{n2}(f)), \end{equation*} since perfect matching has been assumed and hence $G_{n1a}(f)=G_{n1b}(f)=G_{n1}(f)$ and $G_{n2a}(f)=G_{n2b}(f)=G_{n2}(f)$. The noise conductances $G_{ni}(f)$ with $i=1,2$, are frequency dependent since they include both the thermal and the 1/f noise. They are given by \begin{equation*} G_{ni}(f)=\gamma_{ni} G_{mi} + G_{mi}^2 \frac{\rho_i}{W_i\,L_i\,f}, \end{equation*} for $i=1,2$ where $\rho_1=\rho_n$ and $\rho_2=\rho_p$ and \begin{equation*} \gamma_{ni} = \frac{n_i}{2} \end{equation*} in weak inversion and saturation and \begin{equation*} \gamma_{ni} = \frac{2}{3}\,n_i \end{equation*} in strong inversion and saturation.

The noise can be referred to the differential input by dividing $G_{nout}$ by $G_{m1}^2$, resulting in \begin{equation*} R_{nin}(f) \triangleq \frac{G_{nout}}{G_{m1}^2}= R_{nt} + R_{nf}(f) \end{equation*} where $R_{nt}$ is the part of the input-referred noise resistance corresponding to the thermal noise \begin{equation*} R_{nt} = 2\left(\frac{\gamma_{n1}}{G_{m1}} + \gamma_{n2} \frac{G_{m2}}{G_{m1}^2}\right) = \frac{2 \gamma_{n1}}{G_{m1}} \cdot (1 + \eta_{th}), \end{equation*} where \begin{equation*} \eta_{th} = \frac{\gamma_{n2}}{\gamma_{n1}} \frac{G_{m2}}{G_{m1}} \end{equation*} represents the contribution to the input-referred thermal noise of the current mirror relative to the differential pair.

The flicker noise resistance $R_{nf}(f)$ is the part corresponding to the 1/f noise \begin{equation*} R_{nf}(f) = 2 \left[\frac{\rho_n}{W_1 L_1 f} + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \frac{\rho_p}{W_2 L_2 f}\right] = \frac{2 \rho_n}{W_1 L_1 f} \cdot (1 + \eta_{fl}). \end{equation*} where \begin{equation*} \eta_{fl} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \frac{\rho_p}{\rho_n} \frac{W_1 L_1}{W_2 L_2} \end{equation*} represents the contribution to the input-referred flicker noise of the current mirror relative to the differential pair.

In the same way a noise excess factor $\gamma_n$ has been defined for a single transistor, a thermal noise excess factor can also be defined for the complete OTA as \begin{equation*} \gamma_{ota} \triangleq G_m \cdot R_{nt} = \frac{G_{nout,thermal)}}{G_m} = 2\gamma_{n1} \cdot (1 + \eta_{th}) \end{equation*} where $G_m=G_{m1}$ is the OTA differential transconductance. The total input-referred thermal noise resistance then writes \begin{equation*} R_{nt} = \frac{\gamma_{ota}}{G_{m1}}. \end{equation*}

The minimum value of the OTA noise excess factor is obtained for $\eta_{th}=0$ (i.e. neglecting the contribution of the current mirror) and is equal to that of the differential pair only, namely $\gamma_{ota,min} = 2 \gamma_{n1}$. In order to limit the contribution of the current mirror to a minimum, $\eta_{th}$ should be made much smaller than one. Since M1a and M2a (M1b and M2b) share the same bias current $I_{D1}=I_{D2}=I_b/2$, this can be done by biasing the differential pair in weak inversion and the current mirror in strong inversion. In this case, the transconductances of M1a-M1b and M2a-M2b are then given by $G_{m1} = I_{D1}/(n_1 U_T) = I_b/(2 n_1 U_T)$ and $G_{m2} = 2 I_{D2}/(n_2 V_{DSsat2}) = I_b/(n_2 V_{DSsat2})$ with $V_{DSsat2} = V_{P2}$, leading to \begin{equation*} \frac{G_{m2}}{G_{m1}} = \frac{2 n_1 U_T}{n_2 V_{DSsat2}} = \frac{2 n_1 U_T}{n_2 V_{P2}} \cong \frac{2 n_1 U_T}{V_{G2}-V_{TOp}} \end{equation*} The overdrive voltage $V_{G2}-V_{TOp}$ of M2a-M2b has therefore to be chosen much larger than $2 n_1 U_T$. However, it is ultimately limited by the supply voltage $V_{DD}$ and cannot be made too large since it will lead to a large $V_{SG2}$ voltage that, for a given input common mode voltage, may push M1a out of saturation. Replacing $G_{m2}/G_{m1}$ in the expression of $\gamma_{ota}$ results in results in \begin{equation*} \gamma_{ota} = 2\gamma_{n1}\left(1+\frac{\gamma_{n2}}{\gamma_{n1}} \frac{2 n_1 U_T}{V_{G2}-V_{TOp}}\right) = n_1 \left(1+\frac{8 n_2}{3} \frac{U_T}{V_{G2}-V_{TOp}}\right), \end{equation*} where $\gamma_{n1}=n_1/2$ and $\gamma_{n2}=n_2 2/3$. The OTA thermal noise excess factor is therefore minimized by choosing the overdrive voltage $V_{G2}-V_{TOp}$ of M2a-M2b much larger than $8 n_2/3 U_T \cong 4 U_T$ where it has been assumed that $n_2 \cong 3/2$.

The 1/f noise corner frequency $f_k$ is defined as the frequency at which the 1/f noise becomes equal to the thermal noise \begin{equation*} R_{nf}(f_k) = R_{nt} \end{equation*} and is given by \begin{equation*} f_k = \frac{G_{m1}}{\gamma_{ota}} \frac{2 \rho_n}{W_1 L_1} \cdot (1 + \eta_{fl}) = \frac{G_{m1}}{\gamma_{n1}} \frac{\rho_n}{W_1 L_1} \cdot \frac{1+\eta_{fl}}{1+\eta_{th}}. \end{equation*}

The corner frequency can be reduced by increasing $W_1\,L_1$ and $W_2\,L_2$ at the same time to conserve the same $\eta_{fl}$ factor. Of course increasing the area of transistors M1a-M1b and M2a-M2b increases the parasitic capacitance at node 2 and hence decreases the non-dominant pole $\omega_2$.

# Input-referred offset voltage¶

Mismatch between the two transistors of the differential pair M1a-M1b and of the current mirror M2a-M2b causes some current to flow at the output even for a zero differential input voltage $V_{id}=0$. This output current can be compensated by applying a certain differential input voltage defined as the input-referred offset voltage $V_{os}$.

The analysis of the mismatch effects for deriving the variance of the input-referred offset voltage can be done similarly to the noise analysis. We can reuse the expression of the noise output current with \begin{align*} I_{n1a} &= +\frac{\Delta I_{D1}}{2},\\ I_{n1b} &= -\frac{\Delta I_{D1}}{2},\\ I_{n2a} &= -\frac{\Delta I_{D2}}{2},\\ I_{n2b} &= +\frac{\Delta I_{D2}}{2}, \end{align*} and where $\Delta I_{D1}$ and $\Delta I_{D2}$ are the current mismatch in the differential pair and in the current mirror, respectively. The output current due to these current mismatches is then given by \begin{equation*} I_{out} = \Delta I_{D1} + \Delta I_{D2}. \end{equation*} If we only consider the random mismatch, then $\Delta I_{D1}$ and $\Delta I_{D2}$ are random variables. The variance of the offset output current is then given by \begin{equation*} \sigma_{Iout}^2 = \sigma_{\Delta I_{D1}}^2 + \sigma_{\Delta I_{D2}}^2 = I_b^2 \cdot \left(\sigma_{\Delta I_{D1}/I_{D1}}^2 + \sigma_{\Delta I_{D2}/I_{D2}}^2\right) \end{equation*} where \begin{equation*} \sigma_{\Delta I_{Di}/I_{Di}}^2 = \sigma_{\beta i}^2 + \left(\frac{G_{mi}}{I_b}\right)^2\,\sigma_{VTi}^2, \end{equation*} with \begin{align*} \sigma_{\beta i}^2 &= \frac{A_{\beta}^2}{W_i L_i},\\ \sigma_{V_{T0i}}^2 &= \frac{A_{VT}^2}{W_i L_i}. \end{align*} for $i=1,2$. $A_{\beta}$ (usually given in $\% \cdot \mu m$) and $A_{VT}$ (usually given in $mV \cdot \mu m$) are the $\beta$ and threshold matching parameters for the process to be used.

The variance of the output offset current then writes \begin{equation*} \sigma_{Iout}^2 = I_b^2 \cdot \left(\sigma_{\beta 1}^2 + \sigma_{\beta 2}^2\right) + G_{m1}^2\;\sigma_{VT1}^2 + G_{m2}^2\;\sigma_{VT2}^2. \end{equation*}

The variance of the input-referred offset voltage is obtained by dividing the variance of the output offset current by $G_{m1}^2$ resulting in \begin{equation*} \sigma_{Vos}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \left(\sigma_{\beta 1}^2 + \sigma_{\beta 2}^2\right) + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \sigma_{VT2}^2 + \sigma_{VT1}^2. \end{equation*}

We see that the contribution of the $\beta$ mismatch to the input-referred offset voltage can be minimized by choosing $I_b/G_{m1}$ as small as possible (or $G_{m1}/I_b$ as large as possible). This can be done by biasing the transistors of the differential pair in weak inversion. Secondly, the contribution of the $V_T$ mismatch of the current mirror can also be minimized, similarly to what has been done for the noise setting $G_{m2}/G_{m1} \ll 1$ by biasing the differential pair in weak inversion and the current mirror in strong inversion and choosing an overdrive voltage $V_{G2}-V_{TOp}$ of M2a-M2b as large as the voltage headroom allows for.

# Conclusion¶

This notebook presents the detailed analysis of the simple OTA. This analysis allows to derive all the design equations that will be used in the Design Notebook to properly size the circuit in order to achieve a given specification.