The Simple Differential OTA

Verification

Christian Enz

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

# Initialization¶

# Introduction¶

Schematic of the simple differential OTA.

This notebook presents the verification of the design of the simple differential OTA shown above and that was performed in the Design Notebook.

We will first load the process parameters and the specifications. We then will load the bias and the transistors information to evaluate the open-loop transfer function and compare it to the theoretical results obtained in the Design Notebook. We then will check the noise and compare it to the theoretical results obtained in the Design Notebook.

# OTA Characteristics¶

We now will read the results of the sizing procedure performed in the Design Notebook from the Excel file and check whether the specs are achieved.

## Sizing summary¶

### Process parameters¶

    Main physical parameters:
    ═════════════════════════

$T =$ 300 K
$U_T =$ 25.875 mV

    Main process parameters for TSMC 0.18um:
    ════════════════════════════════════════

$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm

    nNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 39 nm
$\Delta L =$ −76 nm

    pNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

### Specifications¶

| Value
--- | ---
Name |
AdcdB | 6.00E+01
GBWmin | 1.00E+06
CL | 1.00E-12
Vosmax | 1.00E-02
PMdeg | 6.00E+01

$A_{dc} =$ 60 dB
$GBW =$ 1 MHz
$V_{osmax} =$ 10 mV
$PM =$ 60 deg

### Bias information¶

| Value
--- | ---
Name |
VDD | 1.80E+00
Ib | 2.50E-07

$I_b =$ 250 nA

### Transistors information¶

| Type | Function | W | L | ID | W/L | Ispec | IC | VP-VS | VG-VT0 | ... | CGSe | CGDe | CGBe | CBSe | CBDe | CGS | CGD | CGB | CBS | CBD
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 1.26E-05 | 3.60E-06 | 2.50E-07 | 3.50E+00 | 2.50E-06 | 9.99E-02 | -5.71E-02 | -4.49E-02 | ... | 4.62E-15 | 4.62E-15 | 0 | 5.18E-14 | 5.18E-14 | 3.58E-14 | 4.62E-15 | 7.51E-14 | 6.03E-14 | 5.18E-14
M1b | n | DP | 1.26E-05 | 3.60E-06 | 2.50E-07 | 3.50E+00 | 2.50E-06 | 9.99E-02 | -5.71E-02 | -4.49E-02 | ... | 4.62E-15 | 4.62E-15 | 0 | 5.18E-14 | 5.18E-14 | 3.58E-14 | 4.62E-15 | 7.51E-14 | 6.03E-14 | 5.18E-14
M2a | p | CM | 2.00E-07 | 6.30E-06 | 2.50E-07 | 3.17E-02 | 5.50E-09 | 4.55E+01 | 3.72E-01 | 2.85E-01 | ... | 6.57E-17 | 6.57E-17 | 0 | 4.64E-15 | 4.64E-15 | 6.60E-15 | 6.57E-17 | 9.61E-16 | 6.64E-15 | 4.64E-15
M2b | p | CM | 2.00E-07 | 6.30E-06 | 2.50E-07 | 3.17E-02 | 5.50E-09 | 4.55E+01 | 3.72E-01 | 2.85E-01 | ... | 6.57E-17 | 6.57E-17 | 0 | 4.64E-15 | 4.64E-15 | 6.60E-15 | 6.57E-17 | 9.61E-16 | 6.64E-15 | 4.64E-15
M3a | n | CM | 2.00E-07 | 1.75E-05 | 5.00E-07 | 1.14E-02 | 8.17E-09 | 6.12E+01 | 4.31E-01 | 3.39E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 1.06E-14 | 1.06E-14 | 1.84E-14 | 7.33E-17 | 2.38E-15 | 1.56E-14 | 1.06E-14
M3b | n | CM | 2.00E-07 | 1.75E-05 | 5.00E-07 | 1.14E-02 | 8.17E-09 | 6.12E+01 | 4.31E-01 | 3.39E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 1.06E-14 | 1.06E-14 | 1.84E-14 | 7.33E-17 | 2.38E-15 | 1.56E-14 | 1.06E-14

6 rows × 33 columns

## Open-loop gain¶

$A_{dc} =$ 62.117 dB
$G_{m1} =$ 6.962 µA/V
$G_{m2} =$ 1.019 µA/V
$f_0 =$ 868.405 Hz
$GBW =$ 1.108 MHz
$f_{p2} =$ 10.717 MHz
$f_{z2} =$ 21.435 MHz

The $GBW$ given above is only an estimation. We can find the $actual $GBW$ accounting for the non-dominant pole using the following script.

$GBW =$ 1.000 MHz (from specifications)
$GBW = \frac{G_{m1}}{C_o} =$ 1.108 MHz (estimation neglecting the effect of the zero)
$GBW = $ 1.104 MHz (estimation including effect of the zero)
$f_0 =$ 868.405 Hz (dominant pole)
$f_{p2} =$ 10.717 MHz (non-dominant pole)

In this case the actual $GBW$ is very close to the estimated one.

We can plot the magnitude and phase of the open-loop gain.

    PGBW = −92.887 deg
    PM = 87.113 deg

## Input-referred noise¶

We can now calculate the noise excess factor of the OTA and the input-referred thermal noise resistance.

$G_{m1} =$ 6.962 µA/V
$G_{m2} =$ 1.019 µA/V
$G_{m1}/G_{m2} =$ 6.835
$\gamma_{n1} =$ 0.653
$\gamma_{n2} =$ 0.841
$\eta_{th} =$ 0.188
$R_{nt} =$ 223 kOhm
$\gamma_{ota} =$ 1.553
$\sqrt{S_{ninth}} =$ 60.774 $\frac{nV}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninth}) =$ -144.326 $\frac{dBv}{\sqrt{Hz}}$

We see that the OTA thermal noise excess factor is only slightly larger than that of the differential pair. This is due to the rather large $G_{m1}/G_{m2}$ ratio.

We can now compute the input-referred flicker noise and the corner frequency.

$(G_{m1}/G_{m2})^2 =$ 46.7
$\rho_p/\rho_n =$ 8.3
$\frac{W_1 \cdot L_1}{W_2 \cdot L_2} =$ 36.0
$\eta_{fl} =$ 5.114
$\sqrt{S_{ninfl}(1\,Hz)} =$ 16.230 $\frac{\mu V}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninfl}(1\,Hz)) =$ -95.794 $\frac{dBv}{\sqrt{Hz}}$
$f_k =$ 70.0 kHz

We can plot the input-reffered noise

## Input-referred offset¶

The variance of the input-referred offset is given by \begin{equation} \sigma_{V_{os}}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \left(\sigma_{\beta_1}^2 + \sigma_{\beta_2}^2\right) + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \sigma_{V_{T02}}^2 + \sigma_{V_{T01}}^2, \end{equation} where \begin{align} \sigma_{\beta_i}^2 &= \frac{A_{\beta}^2}{W_i L_i} \qquad i=1,2,\\ \sigma_{V_{T0i}}^2 &= \frac{A_{VT}^2}{W_i L_i} \qquad i=1,2. \end{align} From the values ocalaculated above we get

$\sigma_{\beta1} =$ 1.485 mV
$\sigma_{\beta2} =$ 8.909 mV
$\sigma_{VT1} =$ 742.392 µV
$\sigma_{VT2} =$ 4.454 mV
$\sigma_{Vos} =$ 1.040 mV

# Simulation results from Smash¶

The theoretical results can be compared with results obtained from simulations performed with Smash. The cells below will run the simulations with Smash. In order to run the simulations you need to have Smash installed in the default directory.

## Saving parameter file¶

We first write the parameter file including all the bias, component values and transistor sizes for this specific design for running the Smash simulations.

    .param VDD=1.8 Vic=0.9 Vos=0.0u Ib=250n
    .param CL=1p
    .param W1=12.60u L1=3.60u W2=0.20u L2=6.30u W3=0.20u L3=17.50u

## Operating point¶

To start we need to check the quiescent voltages and currents and the operating points of all transistors by running a .OP simulation.

    Starting Smash simulation...

    ----------------------------------------------------------------------
    -
    - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020
    - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved.
    -
    ----------------------------------------------------------------------

    Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain
    Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Processing top-level
    Elaborating circuit...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Elaborating circuit (logic)...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Initializing...
    Searching for HZ nets: 0%
    Linking analog resolution matrix...
    Load completed.
    Operating Point
    Operating-Point analysis (trying logarithmic damping heuristics)...
    Iteration    1, residual  9.000e-01 on EINP
    Iteration    2, residual  6.697e-01 on EINP
    Iteration    3, residual  4.657e-01 on EINP
    Iteration    4, residual  2.924e-01 on EINP
    Iteration    5, residual  1.557e-01 on EINP
    Iteration    6, residual  6.180e-02 on EINP
    Iteration    7, residual  1.368e-02 on EINP
    Iteration    8, residual  8.582e-04 on EINP
    Iteration    9, residual  8.898e-05 on VDD
    Iteration   10, residual  2.431e-05 on VDD
    Iteration   11, residual  1.046e-05 on M1A::SI
    Iteration   12, residual  4.478e-06 on M1A::SI
    Iteration   13, residual  1.796e-06 on M1A::SI
    Iteration   14, residual  6.732e-07 on M1A::SI
    Iteration   15, residual  2.228e-07 on M1A::SI
    Iteration   16, residual  5.355e-08 on M1A::DI
    Iteration   17, residual  5.567e-09 on M1A::DI
    Iteration   18, residual  7.751e-11 on M1A::DI
    Iteration   19, residual  1.554e-14 on M1A::DI

    Operating point analysis completed (converged)

    CPU Time:     875ms
    Elapsed Time: 2s 899ms 652us

We can check the operating point information looking the .op file.

    Contents of the op file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    * ----------------------------------------------------------------------
    * Operating point information at 27 degC
    * ----------------------------------------------------------------------
    *
    * Initial state obtained by resetting everything to zero
    *
    * Convergence obtained with initial logarithmic damping heuristics
    * Number of iterations: 19
    *
    * Minimum parallel DC conductance          (.GMINDC   ): 1e-12
    * Minimum parallel transient conductance   (.GMIN     ): 1e-12
    * Minimum capacitance on analog nets       (.CAPAMIN  ): 0
    *
    * ----------------------------------------------------------------------

    * ----------------------------------------------------------------------
    * Analog nets
    * ----------------------------------------------------------------------

    Nets:

        1        =  5.1535619e-01 V.
        2        =  8.7457816e-01 V.
        3        =  9.9652295e-01 V.
        IC       =  9.0000000e-01 V.
        ID       =  0.0000000e+00 V.
        INN      =  9.0000000e-01 V.
        INP      =  9.0000000e-01 V.
        OUT      =  8.7457816e-01 V.
        VDD      =  1.8000000e+00 V.

    Spice internal nets:

        M1A::DI  =  8.7457579e-01 V.
        M1A::SI  =  5.1535856e-01 V.
        M1B::DI  =  8.7457579e-01 V.
        M1B::SI  =  5.1535856e-01 V.
        M2A::DI  =  8.7504695e-01 V.
        M2A::SI  =  1.7995312e+00 V.
        M2B::DI  =  8.7504695e-01 V.
        M2B::SI  =  1.7995312e+00 V.
        M3A::DI  =  9.9627191e-01 V.
        M3A::SI  =  2.5104552e-04 V.
        M3B::DI  =  5.1510558e-01 V.
        M3B::SI  =  2.5061194e-04 V.

    Voltage sources:

        VDD   =  1.8000000e+00 V, -9.9913596e-07 A,  1.798e-06 W.
        VIC   =  9.0000000e-01 V,  0.0000000e+00 A,  0.000e+00 W.
        VID   =  0.0000000e+00 V,  0.0000000e+00 A,  0.000e+00 W.
        EINP  =  0.0000000e+00 V,  0.0000000e+00 A,  0.000e+00 W.
        EINN  =  0.0000000e+00 V,  0.0000000e+00 A,  0.000e+00 W.

    Current sources:

    *   IB  =  5.0000000e-07  A,  8.0347705e-01  V,  4.017e-07 W.

    END_USE_OP_TAG

    * ----------------------------------------------------------------------
    * SPICE Dissipated power
    * ----------------------------------------------------------------------

        Total SPICE power    = 1.3976778e-06 W.

    * ----------------------------------------------------------------------
    * (C) Capacitors
    * ----------------------------------------------------------------------

    CL (DEFAULT, multiplicity = 1)
               VALUE = 1e-12            ,           POWER = 0                ,

    * ----------------------------------------------------------------------
    * (M) Mos transistors
    * ----------------------------------------------------------------------

    OFF:    0
    SUB:    2
    LIN:    0
    SAT:    4

    M1A (NMOS, type NMOS, model EKV 2.6, region SUB (saturation - weak inversion), multiplicity = 1):
      Vds  =  3.59217e-01,  Vgs  =  3.84641e-01,  Vbs  = -2.36950e-06
                WEFF = 1.2639e-05       ,            LEFF = 3.524e-06        ,           POWER = 8.96503e-08      ,              ID = 2.49567e-07      ,
                  GM = 6.83787e-06      ,             GDS = 4.26387e-09      ,            GMBS = 2.00962e-06      ,           VDSAT = 0.119528         ,
                 VTH = 0.463077         ,          DELVTO = 0               D,              QD = -3.84292e-16     ,              QG = 1.95932e-13      ,
                  QB = -1.94795e-13     ,              QS = -7.52805e-16     ,             CGG = 1.06412e-13      ,             CGD = 3.34032e-17      ,
                 CGS = -2.9846e-14      ,             CGB = -7.65993e-14     ,             CBG = -7.6701e-14      ,             CBD = -2.40275e-17     ,
                 CBS = -8.38629e-15     ,             CBB = 8.51113e-14      ,             CDG = -1.01672e-14     ,             CDD = -3.19346e-18     ,
                 CDS = 1.30827e-14      ,             CDB = -2.91228e-15     ,            QBDJ = 5.64345e-15      ,            QBSJ = 3.92286e-20      ,
                CBDJ = 9.41406e-15      ,            CBSJ = 1.03783e-14      ,

    M1B (NMOS, type NMOS, model EKV 2.6, region SUB (saturation - weak inversion), multiplicity = 1):
      Vds  =  3.59217e-01,  Vgs  =  3.84641e-01,  Vbs  = -2.36950e-06
                WEFF = 1.2639e-05       ,            LEFF = 3.524e-06        ,           POWER = 8.96503e-08      ,              ID = 2.49567e-07      ,
                  GM = 6.83787e-06      ,             GDS = 4.26387e-09      ,            GMBS = 2.00962e-06      ,           VDSAT = 0.119528         ,
                 VTH = 0.463077         ,          DELVTO = 0               D,              QD = -3.84292e-16     ,              QG = 1.95932e-13      ,
                  QB = -1.94795e-13     ,              QS = -7.52805e-16     ,             CGG = 1.06412e-13      ,             CGD = 3.34032e-17      ,
                 CGS = -2.9846e-14      ,             CGB = -7.65993e-14     ,             CBG = -7.6701e-14      ,             CBD = -2.40275e-17     ,
                 CBS = -8.38629e-15     ,             CBB = 8.51113e-14      ,             CDG = -1.01672e-14     ,             CDD = -3.19346e-18     ,
                 CDS = 1.30827e-14      ,             CDB = -2.91228e-15     ,            QBDJ = 5.64345e-15      ,            QBSJ = 3.92286e-20      ,
                CBDJ = 9.41406e-15      ,            CBSJ = 1.03783e-14      ,

    M2A (PMOS, type PMOS, model EKV 2.6, region SAT (saturation - strong inversion), multiplicity = 1):
      Vds  = -9.24484e-01,  Vgs  = -9.24953e-01,  Vbs  =  4.68793e-04
                WEFF = 2.54e-07         ,            LEFF = 6.228e-06        ,           POWER = 2.30956e-07      ,              ID = -2.49566e-07     ,
                  GM = 9.70396e-07      ,             GDS = 7.81512e-10      ,            GMBS = 3.51519e-07      ,           VDSAT = -0.44552         ,
                 VTH = -0.4611          ,          DELVTO = 0               D,              QD = 1.34352e-15      ,              QG = -1.21853e-14     ,
                  QB = 8.73706e-15      ,              QS = 2.10477e-15      ,             CGG = 9.28558e-15      ,             CGD = 8.41758e-19      ,
                 CGS = -8.20822e-15     ,             CGB = -1.0782e-15      ,             CBG = -1.29687e-15     ,             CBD = -1.16253e-19     ,
                 CBS = -2.14774e-15     ,             CBB = 3.44473e-15      ,             CDG = -3.18261e-15     ,             CDD = -2.89033e-19     ,
                 CDS = 4.12339e-15      ,             CDB = -9.40483e-16     ,            QBDJ = -3.8861e-16      ,            QBSJ = -2.29291e-19     ,
                CBDJ = 3.32077e-16      ,            CBSJ = 4.38318e-16      ,

    M2B (PMOS, type PMOS, model EKV 2.6, region SAT (saturation - strong inversion), multiplicity = 1):
      Vds  = -9.24484e-01,  Vgs  = -9.24953e-01,  Vbs  =  4.68793e-04
                WEFF = 2.54e-07         ,            LEFF = 6.228e-06        ,           POWER = 2.30956e-07      ,              ID = -2.49566e-07     ,
                  GM = 9.70396e-07      ,             GDS = 7.81512e-10      ,            GMBS = 3.51519e-07      ,           VDSAT = -0.44552         ,
                 VTH = -0.4611          ,          DELVTO = 0               D,              QD = 1.34352e-15      ,              QG = -1.21853e-14     ,
                  QB = 8.73706e-15      ,              QS = 2.10477e-15      ,             CGG = 9.28558e-15      ,             CGD = 8.41758e-19      ,
                 CGS = -8.20822e-15     ,             CGB = -1.0782e-15      ,             CBG = -1.29687e-15     ,             CBD = -1.16253e-19     ,
                 CBS = -2.14774e-15     ,             CBB = 3.44473e-15      ,             CDG = -3.18261e-15     ,             CDD = -2.89033e-19     ,
                 CDS = 4.12339e-15      ,             CDB = -9.40483e-16     ,            QBDJ = -3.8861e-16      ,            QBSJ = -2.29291e-19     ,
                CBDJ = 3.32077e-16      ,            CBSJ = 4.38318e-16      ,

    M3A (NMOS, type NMOS, model EKV 2.6, region SAT (saturation - strong inversion), multiplicity = 1):
      Vds  =  9.96021e-01,  Vgs  =  9.96272e-01,  Vbs  = -2.51046e-04
                WEFF = 2.39e-07         ,            LEFF = 1.7424e-05       ,           POWER = 4.98261e-07      ,              ID = 4.99998e-07      ,
                  GM = 1.70971e-06      ,             GDS = 6.73625e-10      ,            GMBS = 4.99459e-07      ,           VDSAT = 0.510419         ,
                 VTH = 0.45714          ,          DELVTO = 0               D,              QD = -4.1883e-15      ,              QG = 3.1353e-14       ,
                  QB = -2.06459e-14     ,              QS = -6.51879e-15     ,             CGG = 2.4385e-14       ,             CGD = 1.59079e-18      ,
                 CGS = -2.19217e-14     ,             CGB = -2.46483e-15     ,             CBG = -3.05866e-15     ,             CBD = -1.97028e-19     ,
                 CBS = -4.95867e-15     ,             CBB = 8.01752e-15      ,             CDG = -8.50627e-15     ,             CDD = -5.5592e-19      ,
                 CDS = 1.07163e-14      ,             CDB = -2.20943e-15     ,            QBDJ = 5.22219e-16      ,            QBSJ = 1.42727e-19      ,
                CBDJ = 3.09902e-16      ,            CBSJ = 3.56385e-16      ,

    M3B (NMOS, type NMOS, model EKV 2.6, region SAT (saturation - strong inversion), multiplicity = 1):
      Vds  =  5.14855e-01,  Vgs  =  9.96272e-01,  Vbs  = -2.50612e-04
                WEFF = 2.39e-07         ,            LEFF = 1.7424e-05       ,           POWER = 2.57233e-07      ,              ID = 4.99135e-07      ,
                  GM = 1.69574e-06      ,             GDS = 1.61414e-08      ,            GMBS = 4.96095e-07      ,           VDSAT = 0.510394         ,
                 VTH = 0.457168         ,          DELVTO = 0               D,              QD = -4.19386e-15     ,              QG = 3.13583e-14      ,
                  QB = -2.06444e-14     ,              QS = -6.52e-15        ,             CGG = 2.45578e-14      ,             CGD = -2.23494e-16     ,
                 CGS = -2.19089e-14     ,             CGB = -2.42541e-15     ,             CBG = -3.01987e-15     ,             CBD = -5.11858e-17     ,
                 CBS = -4.95582e-15     ,             CBB = 8.02688e-15      ,             CDG = -8.6719e-15      ,             CDD = 2.15129e-16      ,
                 CDS = 1.07044e-14      ,             CDB = -2.24758e-15     ,            QBDJ = 2.78702e-16      ,            QBSJ = 1.4248e-19       ,
                CBDJ = 3.25779e-16      ,            CBSJ = 3.56385e-16      ,

    * ----------------------------------------------------------------------
    * (R) Resistors
    * ----------------------------------------------------------------------

Looking at the .op file, we see that all transistors are in saturation. We also see that the quiescent output voltage is given by

$V_{outq} =$ 874.578 mV

which is close to the input common mode $V_{ic}=0.9\,V$. This confirms that the OTA is not saturated by its proper systematic offset. We can now proceed with the DC simulation.

## Large-signal differential transfer characteristic¶

We now simulate the large-signal differential transfer characteristic to extract the output voltage swing.

    .param Vidmin=-9.000e-01 Vidmax=9.000e-01 dVid=2.000e-03
    Starting Smash simulation...

    ----------------------------------------------------------------------
    -
    - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020
    - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved.
    -
    ----------------------------------------------------------------------

    Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain
    Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Processing top-level
    Elaborating circuit...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Elaborating circuit (logic)...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Initializing...
    Searching for HZ nets: 0%
    Linking analog resolution matrix...
    Load completed.
    DC Transfer - VID.Value
    Operating-Point analysis (trying logarithmic damping heuristics)...
    Number of iterations:   0
    DC transfer analysis completed
    Launch Measurements: 12
    End Measurements

    CPU Time:     984ms 375us
    Elapsed Time: 3s 672ms 284us

    VDD = 1.8 V
    Vic = 0.9 V
    Voutq = 0.875 V
    Vos = 84.151 uV
    Voutmax = 1.800 V
    Voutmin = 0.099 V
    Vswing = 1.701 V

The extracted output voltage swing does actually not correspond to the swing of the linear part. We need to zoom into the linear gain region.

    .param Vidmin=-5.000e-04 Vidmax=5.000e-04 dVid=1.000e-06
    Starting Smash simulation...

    ----------------------------------------------------------------------
    -
    - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020
    - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved.
    -
    ----------------------------------------------------------------------

    Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain
    Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Processing top-level
    Elaborating circuit...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Elaborating circuit (logic)...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Initializing...
    Searching for HZ nets: 0%
    Linking analog resolution matrix...
    Load completed.
    DC Transfer - VID.Value
    Operating-Point analysis (trying logarithmic damping heuristics)...
    Number of iterations:   0
    DC transfer analysis completed
    Launch Measurements: 12
    End Measurements

    CPU Time:     1s 62ms 500us
    Elapsed Time: 3s 914ms 918us

    VDD = 1.8 V
    Vic = 0.9 V
    Voutq = 0.875 V
    Vos = 18.554 uV
    Voutmax = 1.396 V
    Voutmin = 0.642 V
    Vswing = 0.754 V

The output voltage swing is actually even smaller than the one extracted above. It is about $V_{swing}=0.55\,V$ which is rather small. We will see that the output swing can be extended with different OTA architectures.

The offset voltage needed to bring the output voltage to $V_{ic}$ is extracted as $V_{os}=18.5\,\mu V$. We save it to the bias information file for further AC simulations.

    .param VDD=1.8 Vic=0.9 Vos=18.554u Ib=250n
    .param CL=1p
    .param W1=12.60u L1=3.60u W2=0.20u L2=6.30u W3=0.20u L3=17.50u

## Open-loop gain¶

After having checked the operating point information and making sure that the OTA output is not saturated by extracting the required offset voltage for bringing the output operating point to $V_{ic}$, we can now perform the AC simulation.

    Starting Smash simulation...

    ----------------------------------------------------------------------
    -
    - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020
    - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved.
    -
    ----------------------------------------------------------------------

    Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain
    Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Processing top-level
    Elaborating circuit...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Elaborating circuit (logic)...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Initializing...
    Searching for HZ nets: 0%
    Linking analog resolution matrix...
    Load completed.
    Operating-Point analysis (trying logarithmic damping heuristics)...
    Iteration    1, residual  9.000e-01 on EINP
    Iteration    2, residual  6.697e-01 on EINP
    Iteration    3, residual  4.657e-01 on EINP
    Iteration    4, residual  2.924e-01 on EINP
    Iteration    5, residual  1.557e-01 on EINP
    Iteration    6, residual  6.180e-02 on EINP
    Iteration    7, residual  1.368e-02 on EINP
    Iteration    8, residual  8.584e-04 on EINP
    Iteration    9, residual  8.898e-05 on VDD
    Iteration   10, residual  2.431e-05 on VDD
    Iteration   11, residual  1.046e-05 on M1A::SI
    Iteration   12, residual  4.477e-06 on M1A::SI
    Iteration   13, residual  1.795e-06 on M1A::SI
    Iteration   14, residual  6.730e-07 on M1A::SI
    Iteration   15, residual  2.227e-07 on M1A::SI
    Iteration   16, residual  5.353e-08 on M1A::DI
    Iteration   17, residual  5.562e-09 on M1A::DI
    Iteration   18, residual  7.736e-11 on M1A::DI
    Iteration   19, residual  1.549e-14 on M1B::DI

    Operating point analysis completed (converged)
    Small Signal
    Small signal analysis completed
    Launch Measurements: 12
    End Measurements

    CPU Time:     1s 171ms 875us
    Elapsed Time: 5s 809ms 292us

    Adc = 62.832 dB
    GBW = 1.056e+06 Hz
    Phase at GBW = -97.156 deg
    Phase margin = 82.844 deg

We see a very good match between the small-signal simulations and the theoretical results except at higher frequency where additional poles due to parasitic capacitances that have not been accounted for introduce additional phase shift.

## Input-referred noise¶

We can compare the theoretical input-referred noise to that obtained from simulations.

    Starting Smash simulation...

    ----------------------------------------------------------------------
    -
    - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020
    - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved.
    -
    ----------------------------------------------------------------------

    Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain
    Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Jupyter Notebooks\Simple OTA\Simple OTA (VS)\Simulations\smash\Gain\Simple_OTA.pat
    Processing top-level
    Elaborating circuit...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Elaborating circuit (logic)...
    Elaborating circuit (creating devices)...
    Elaborating circuit (elaborating devices)...
    Initializing...
    Searching for HZ nets: 0%
    Linking analog resolution matrix...
    Load completed.
    Operating-Point analysis (trying logarithmic damping heuristics)...
    Iteration    1, residual  9.000e-01 on EINP
    Iteration    2, residual  6.697e-01 on EINP
    Iteration    3, residual  4.657e-01 on EINP
    Iteration    4, residual  2.924e-01 on EINP
    Iteration    5, residual  1.557e-01 on EINP
    Iteration    6, residual  6.180e-02 on EINP
    Iteration    7, residual  1.368e-02 on EINP
    Iteration    8, residual  8.584e-04 on EINP
    Iteration    9, residual  8.898e-05 on VDD
    Iteration   10, residual  2.431e-05 on VDD
    Iteration   11, residual  1.046e-05 on M1A::SI
    Iteration   12, residual  4.477e-06 on M1A::SI
    Iteration   13, residual  1.795e-06 on M1A::SI
    Iteration   14, residual  6.730e-07 on M1A::SI
    Iteration   15, residual  2.227e-07 on M1A::SI
    Iteration   16, residual  5.353e-08 on M1A::DI
    Iteration   17, residual  5.562e-09 on M1A::DI
    Iteration   18, residual  7.736e-11 on M1A::DI
    Iteration   19, residual  1.549e-14 on M1B::DI

    Operating point analysis completed (converged)
    Noise
    Noise analysis completed
    Launch Measurements: 12
    End Measurements

    CPU Time:     1s 15ms 625us
    Elapsed Time: 6s 716ms 753us

We can observe that the simulated input-referred noise perfectly the theoretical prediction.

In Smash we can look at the thermal and flicker noise separately. We can compare the contributions of differential pair and the current mirror to the input-referred thermal noise PSD.

The contribution of the current mirror to the input-referred thermal noise PSD is about 7 dB lower (about 5 times lower) which is slightly lower than the value $1/\eta_{th} \cong 5.3$ obtained in the design phase. It is nevertheless large enough for the current mirror to contribute only marginally to the input-referred thermal noise.

We can also check the contributions of the differential pair and the current mirror to the input-referred flicker noise.

The situation is different for the input-referred flicker noise. Indeed, the current mirror is now dominating over the differential pair despite the large $G_{m1}/G_{m2}$ ratio. This is due to the flicker noise of the pMOS transistor being about 8 times larger than that of the nMOS for this given technology.

## Input-referred offset voltage¶

The standard deviation of the random input-referred offset voltage can be simulated in Smash using Monte-Carlo (MC) simulation with 1000 runs. Note that the matching parameters have to be converted to dispersion parameters according to \begin{align*} SIGMAV &= \frac{A_{VT}}{\sqrt{2}},\\ SIGMAI &= \frac{A_{\beta}}{\sqrt{2}}. \end{align*} for both NMOS and pMOS.

MC simulation of the open-loop transfer characteristic for extracting the offset voltage.

The offset voltage is first extracted from the open-loop circuit as shown in the above figure. The results of the MC simulation is $\sigma_{Vos} = 1.07\,mV$ which is consistent with the dispersion simulation $\sigma_{Vos} = 1.05\,mV$ provided by Smash and close to the theoretical estimations $\sigma_{Vos} = 1.08\,mV$.

MC simulation using a closed-loop configuration for extracting the offset voltage.

For high gain amplifiers, it is also possible to measure the offset by putting the OPAMP in a closed loop as shown in the above figure. The results of the MC simulation is $\sigma_{Vos} = 1.07\,mV$ which is consistent with the dispersion simulation $\sigma_{Vos} = 1.05\,mV$ provided by Smash and close to the theoretical estimations $\sigma_{Vos} = 1.08\,mV$.

MC closed-loop simulation of the contributions of the differential pair and the current mirror to the input-referred offset.

Contribution of the various transistors to the input-referred offset is shown in the above figure. It confirms that the differential pair is the dominant contributor to the offset voltage.

## Power consumption¶

The total power consumption is given by

$I_{tot} =$ 1.0 µA
$P =$ 1.8 µW

# Simulation results from ngspice¶

The theoretical results can also be compared with results obtained from simulations performed with ngspice. The cells below will run the simulations with ngspice. In order to run the simulations you need to have ngspice installed. Please refer to the moodel site for full instructions.

## Saving parameter file¶

We first write the parameter file for this specific design for running the ngspice simulations.

    .param VDD=1.8 Vic=0.9 Vos=0.0u Ib=250n
    .param CL=1p
    .param W1=12.60u L1=3.60u W2=0.20u L2=6.30u W3=0.20u L3=17.50u

## Operating point¶

    Starting ngspice simulation...

    Simulation executed successfully.

    ******
    ** ngspice-43 : Circuit level simulation program
    ** Compiled with KLU Direct Linear Solver
    ** The U. C. Berkeley CAD Group
    ** Copyright 1985-1994, Regents of the University of California.
    ** Copyright 2001-2024, The ngspice team.
    ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
    ** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
    ** Creation Date: Jul 13 2024   10:19:33
    ******

    Batch mode

    Comments and warnings go to log-file: ./Simulations/ngspice/Gain/Simple_OTA.op.log

    Contents of the log file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed
    wrdata: too few args.

    Note: No compatibility mode selected!

    Circuit: simulation of the simple ota designed with the ekv 2.6 model

    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1

    Node data saved to file ./Simulations/ngspice/Gain/simple_ota.op.ic
    Note: Simulation executed from .control section

The voltages at the various circuit nodes are given below.

| Node name | Node voltage
--- | --- | ---
0 | v(2) | 8.74E-01
1 | v(inp) | 9.00E-01
2 | v(1) | 5.15E-01
3 | v(out) | 8.74E-01
4 | v(inn) | 9.00E-01
5 | v(vdd) | 1.80E+00
6 | v(3) | 9.97E-01
7 | v(vss) | 0.00E+00
8 | v(ic) | 9.00E-01
9 | v(id) | 0.00E+00

We see that the output voltage is actually set by the drain and gate voltage of M2a (voltage at node 2 v(2)) because the currents in the two branches are identical and therefore the drain voltages of M2b and M1b must be equal to the drain voltages of M2a and M1a. This means that M2b and M1b are in saturation. The quiescent output voltage is extracted below.

$V_{outq} =$ 874.414 mV

The operating point information for all transistors can be extracted from the .op file.

| Transistor | ID | Ispec | IC | VDsat | n | Gm | Gms | Gds | Gmb | Rn | Vnth | gamman | Vnfl at 1Hz
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
0 | M1a | 2.50E-07 | 2.58E-06 | 9.66E-02 | 1.20E-01 | 1.27E+00 | 6.84E-06 | 8.85E-06 | 4.27E-09 | 2.01E-06 | 9.84E+04 | 4.04E-08 | 6.73E-01 | 4.64E-06
1 | M1b | 2.50E-07 | 2.58E-06 | 9.66E-02 | 1.20E-01 | 1.27E+00 | 6.84E-06 | 8.85E-06 | 4.27E-09 | 2.01E-06 | 9.84E+04 | 4.04E-08 | 6.73E-01 | 4.64E-06
2 | M2a | 2.50E-07 | 5.70E-09 | 4.39E+01 | 4.46E-01 | 1.31E+00 | 9.72E-07 | 1.32E-06 | 7.84E-10 | 3.52E-07 | 9.29E+05 | 1.24E-07 | 9.03E-01 | 7.10E-05
3 | M2b | 2.50E-07 | 5.70E-09 | 4.39E+01 | 4.46E-01 | 1.31E+00 | 9.72E-07 | 1.32E-06 | 7.84E-10 | 3.52E-07 | 9.29E+05 | 1.24E-07 | 9.03E-01 | 7.10E-05
4 | M3a | 5.00E-07 | 8.03E-09 | 6.24E+01 | 5.12E-01 | 1.27E+00 | 1.71E-06 | 2.21E-06 | 6.74E-10 | 5.00E-07 | 5.12E+05 | 9.21E-08 | 8.76E-01 | 1.52E-05
5 | M3b | 4.99E-07 | 8.02E-09 | 6.24E+01 | 5.12E-01 | 1.27E+00 | 1.70E-06 | 2.21E-06 | 1.60E-08 | 4.96E-07 | 5.20E+05 | 9.28E-08 | 8.83E-01 | 1.52E-05

We can check the bias voltages and operating region of each transistor below.

| Type | Function | ID | IC | VG | VS | VD | VDS | VDsat | Region | Saturation
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 2.496E-07 | 9.665E-02 | 3.846E-01 | 0.000E+00 | 3.591E-01 | 3.591E-01 | 1.195E-01 | WI | sat
M1b | n | DP | 2.496E-07 | 9.665E-02 | 3.846E-01 | 0.000E+00 | 3.591E-01 | 3.591E-01 | 1.195E-01 | WI | sat
M2a | p | CM | 2.496E-07 | 4.394E+01 | 9.256E-01 | 0.000E+00 | 9.256E-01 | 9.256E-01 | 4.464E-01 | SI | sat
M2b | p | CM | 2.496E-07 | 4.394E+01 | 9.256E-01 | 0.000E+00 | 9.256E-01 | 9.256E-01 | 4.464E-01 | SI | sat
M3a | n | CM | 5.000E-07 | 6.236E+01 | 9.966E-01 | 0.000E+00 | 9.966E-01 | 9.966E-01 | 5.120E-01 | SI | sat
M3b | n | CM | 4.991E-07 | 6.236E+01 | 9.966E-01 | 0.000E+00 | 5.154E-01 | 5.154E-01 | 5.119E-01 | SI | sat

All transistors are biased in saturation. The operating points looks fine. We can now proceed with the large-signal DC simulation.

## Large-signal differential transfer characteristic¶

We now simulate the DC differential transfer characteristic. We can then extract the systematic offset voltage that is required to bring the output voltage back to $V_{ic}$.

    Starting NGSpice simulation...

    Simulation executed successfully.

    ******
    ** ngspice-43 : Circuit level simulation program
    ** Compiled with KLU Direct Linear Solver
    ** The U. C. Berkeley CAD Group
    ** Copyright 1985-1994, Regents of the University of California.
    ** Copyright 2001-2024, The ngspice team.
    ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
    ** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
    ** Creation Date: Jul 13 2024   10:19:33
    ******

    Batch mode

    Comments and warnings go to log-file: ./Simulations/ngspice/Gain/Simple_OTA.dc.log

    Contents of the log file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed
    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed

    Note: No compatibility mode selected!

    Circuit: simulation of the simple ota designed with the ekv 2.6 model

    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1
    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 901
    vos                 =  8.470761e-05
    voutmax             =  1.800000e+00 at=  9.000000e-01
    voutmin             =  9.909677e-02 at=  -9.000000e-01
    Note: Simulation executed from .control section

    VDD = 1.8 V
    Vic = 0.9 V
    Voutq = 0.874 V
    Vos = 84.708 uV
    Voutmax = 1.800 V
    Voutmin = 0.099 V
    Vswing = 1.701 V

We can now zoom into the high gain region to extract a more accurate value of the offset voltage.

    Starting NGSpice simulation...

    Simulation executed successfully.

    ******
    ** ngspice-43 : Circuit level simulation program
    ** Compiled with KLU Direct Linear Solver
    ** The U. C. Berkeley CAD Group
    ** Copyright 1985-1994, Regents of the University of California.
    ** Copyright 2001-2024, The ngspice team.
    ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
    ** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
    ** Creation Date: Jul 13 2024   10:19:33
    ******

    Batch mode

    Comments and warnings go to log-file: ./Simulations/ngspice/Gain/Simple_OTA.dc.log

    Contents of the log file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed
    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed

    Note: No compatibility mode selected!

    Circuit: simulation of the simple ota designed with the ekv 2.6 model

    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1
    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1001
    vos                 =  1.865937e-05
    voutmax             =  1.395844e+00 at=  5.000000e-04
    voutmin             =  6.417267e-01 at=  -5.000000e-04
    Note: Simulation executed from .control section

    VDD = 1.8 V
    Vic = 0.9 V
    Voutq = 0.874 V
    Vos = 18.659 uV
    Voutmax = 1.396 V
    Voutmin = 0.642 V
    Vswing = 0.754 V

The output voltage swing is actually even smaller than the one extracted above. It is about $V_{swing}=0.55\,V$ which is rather small. We will see that the output swing can be extended with different OTA architectures.

The offset voltage needed to bring the output voltage to $V_{ic}$ is extracted as $V_{os}=18.5\,\mu V$. We save it to the bias information file for further AC simulations.

    .param VDD=1.8 Vic=0.9 Vos=18.659u Ib=250n
    .param CL=1p
    .param W1=12.60u L1=3.60u W2=0.20u L2=6.30u W3=0.20u L3=17.50u

## Open-loop gain¶

After having checked the operating point information and making sure that the OTA output is not saturated, we can proceed with the open-loop gain simulation. Note that for higher DC gain OTAs, the output might saturate due to asymmetries in the operating points induced by output conductances. In this case, a DC input voltage (that corresponds to the DC value of parameter Vos of $V_{id}$ in the netlist) needs to be added in order to bring the output voltage to the desired quiescent voltage. It will not be the case for the simple OTA and we therefore can keep $V_{os}=0\,V$.

    Starting NGSpice simulation...

    Simulation executed successfully.

    ******
    ** ngspice-43 : Circuit level simulation program
    ** Compiled with KLU Direct Linear Solver
    ** The U. C. Berkeley CAD Group
    ** Copyright 1985-1994, Regents of the University of California.
    ** Copyright 2001-2024, The ngspice team.
    ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
    ** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
    ** Creation Date: Jul 13 2024   10:19:33
    ******

    Batch mode

    Comments and warnings go to log-file: ./Simulations/ngspice/Gain/Simple_OTA.ac.log

    Contents of the log file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed
    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed

    Note: No compatibility mode selected!

    Circuit: simulation of the simple ota designed with the ekv 2.6 model

    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1
    ASCII raw file "./Simulations/ngspice/Gain/Simple_OTA.ac.op"
    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 288
    adc                 =  6.283966e+01 at=  1.000000e+01
    gbw                 =  1.066642e+06
    pgbw                =  -9.555699e+01
    Note: Simulation executed from .control section

    Adc = 62.840 dB
    GBW = 1.067e+06 Hz
    Phase at GBW = -95.557 deg
    Phase margin = 84.443 deg

We see a very good match between the small-signal simulations and the theoretical results except at higher frequency where additional poles due to parasitic capacitances that have not been accounted for introduce additional phase shift.

## Input-referred noise¶

We can compare the theoretical input-referred noise to that obtained from simulations.

    Starting NGSpice simulation...

    Simulation executed successfully.

    ******
    ** ngspice-43 : Circuit level simulation program
    ** Compiled with KLU Direct Linear Solver
    ** The U. C. Berkeley CAD Group
    ** Copyright 1985-1994, Regents of the University of California.
    ** Copyright 2001-2024, The ngspice team.
    ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
    ** Please file your bug-reports at https://ngspice.sourceforge.io/bugrep.html
    ** Creation Date: Jul 13 2024   10:19:33
    ******

    Batch mode

    Comments and warnings go to log-file: ./Simulations/ngspice/Gain/Simple_OTA.nz.log

    Contents of the log file:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed
    Using SPARSE 1.3 as Direct Linear Solver
    Note: Starting dynamic gmin stepping
    Note: Dynamic gmin stepping completed

    Note: No compatibility mode selected!

    Circuit: simulation of the simple ota designed with the ekv 2.6 model

    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 1
    Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

    No. of Data Rows : 288

    No. of Data Rows : 1
    Note: Simulation executed from .control section

We can observe that the simulated input-referred noise perfectly the theoretical prediction.

Unfortunately, with ngspice it is not that straightforward to separate thermal and flicker. It is also not that easy to see the contributions of individual transistors.

# Conclusion¶

This notebook presented the verification of the design performed in the Design notebook using Smash simulations. The results obtained for the the open-loop transfer function are very close to the theoretical prediction. In particular the $GBW$ and phase margin are slightly larger than the target. The input referred-noise is also close. The input-referred thermal noise is very close to the theoretical estimation, whereas the simulation flicker noise is slightly lower than the theoretical estimation. This leads to a extracted corner frequency that is lower than the theoretical prediction.